1. Field of the Invention
The present invention relates to a multilayer capacitor that realizes reduced total inductance with reduced manufacturing cost, and more particularly, to that suitable for use as a multilayer ceramic chip capacitor capable of reducing voltage fluctuation of a power source of a CPU.
2. Description of the Related Art
In recent years, due to an improved processing speed and a higher integration degree of a CPU (central processing unit) used for a data processor, its operating frequency is becoming higher and its current consumption is remarkably increasing. In accordance therewith, the operating voltage has been on the decreasing trend due to reduced power consumption. This has caused the occurrence of a higher-speed and larger current fluctuation in a power source for supplying power to the CPU, and it has become very difficult to control voltage fluctuation accompanying this current fluctuation, within an allowable value range of the power source.
Therefore, as a measure for stabilizing the power source, a multilayer capacitor as a smoothing capacitor is disposed in the vicinity of the CPU in the state of being connected to the power source and has come in frequent use. By quick charge/discharge at the time of a high-speed transient current fluctuation, the multilayer capacitor supplies a current to the CPU, thereby reducing the voltage fluctuation of the power source.
However, today's trend toward a still higher operating frequency of the CPU has resulted in higher-speed and larger current fluctuation, and consequently, equivalent series inductance (ESL) that the multilayer capacitor as a smoothing capacitor itself has become relatively large. As a result, total inductance including this equivalent series inductance gives a significant influence to the voltage fluctuation of the power source.
To solve this problem, as a structure of a conventional multilayer capacitor realizing reduced ESL, one disclosed in, for example, Japanese Patent Application Laid-open No. 2001-284170 (hereinafter, referred to as a patent document 1) is known. Specifically, this patent document 1 discloses a structure such that a plurality of terminal electrodes are disposed on each of four side faces of a multilayer capacitor in a rectangular parallelepiped shape, thereby realizing reduced ESL.
Further, Japanese Patent Application Laid-open No. 2001-189234, Japanese Patent Application Laid-open No. Hei 7-326536, and Japanese Patent Application Laid-open No. 2003-59755 (hereinafter, referred to as patent documents 2 to 4) disclose a multilayer capacitor adopting a structure such that external electrodes separated in an island form are disposed on at least one face out of upper and lower faces of the multilayer capacitor and the external electrodes are connected to internal electrodes by columnar through-hole electrodes. Specifically, in the inventions disclosed in the patent documents 2 to 4, the multilayer capacitor is directly connectable to pins serving as terminal electrodes disposed on a lower face side of a CPU, via these external electrodes, thereby reducing total inductance of a circuit having this multilayer capacitor.
However, in a multilayer capacitor in which a plurality of terminal electrodes are disposed on each of four side faces to be connected to the periphery of a CPU as in the patent document 1 described above, ESL cannot be sufficiently reduced, which has posed a limit on reduction in the total inductance.
On the other hand, a multilayer capacitor having external electrodes in an island form as in the patent documents 2 to 4 can respond to a higher speed of a CPU since total inductance is reduced. However, in manufacturing this multilayer capacitor, it has been necessary to produce a large number of slender through-holes inside the multilayer capacitor. This as a result makes the manufacture of the multilayer capacitor difficult, which has been a cause of increasing manufacturing cost.